With the advent of mobile computing, a demand was created for circuits and methods that provide greater control over clocking signals. This demand arose because of the strong correlation between the clock signal frequency at which the microprocessor operates, and the total power dissipation of the system. In other words, in a mobile computer environment it is desirable to have the capability of slowing down the operating clock frequency of the processor during times of relative inactivity or non-use. Doing so reduces the power drain on the computer's battery. When normal operating activity resumes, the clocking frequency should then be increased to provide for maximum system performance.
In the past, various power management schemes have been designed for use in microprocessor-controlled computer systems. By way of example, the popular Pentium.RTM. and Pentium II.RTM. processors define a power management state in which the processor's internal clock signal is stopped or halted. This state is initiated by assertion of an external input pin, known as the STPCLK# input. When the STPCLK# is asserted, the processor initiates a sequence of events that results in halting the internal clock signal. This mechanism is described in detail in U.S. Pat. No. 5,473,767, which patent is assigned to the assignee of the present application.
FIG. 1 is a state diagram illustrating the operation of the prior art mechanism for controlling the internal clock signal of the processor. The sequence of events shown in FIG. 1 begins with the assertion of the STPCLK# signal at a pin of the processor as shown by ellipse 10. When the STPCLK# signal pin is asserted, a microflag in the microcode engine of the processor gets set; it also signals an internal state machine in a dedicated STP_CLK logic block. An interrupt prioritizer insures that the microcode engine recognizes this as an interrupt to be asserted at the next instruction boundary. In this manner, the internal clock signal of the processor is not halted until after the end of the current instruction. This is represented in FIG. 5 by decision block 11.
Next, all of the bus cycles within the processor's internal bus unit (BU) are flushed and then idled. This is shown in FIG. 1 by block 12, which indicates that the bus unit of the processor is emptied of bus cycles. At this point, the microcode indicates to the BU to execute a STOP_CLK acknowledgement bus cycle. This is shown in FIG. 1 by block 13. Finally, the internal pipelines of the processor are emptied, as represented in block 14.
After that, the pipelines have been emptied, microcode indicates to the STP_CLK logic block to stop the internal clock. This is accomplished by asserting a STP_MY_CLK signal. This signal basically masks the internal clock signal of the processor through an AND gate function.
When the STPCLK# pin is de-asserted, the STP_CLK logic block automatically restarts the internal clock by deactivating the STP_MY_CLK signal. It should be understood that during the time that the internal clock signal is halted, the phase lock loop circuit that produces the internal clock signal typically remains active. After the STPCLK# has been de-asserted, the microcode engine of the processor detects that the internal clock signal is once again active (block 16), and generates a RETURN (block 17).
The prior art Pentium.RTM. processors also include a feature for changing the operating clock frequency provided to the internal logic. However, this can only be accomplished by resetting the processor. When the processor is RESET the state of four pins on the front side of the processor bus are used to latch in a new clock frequency ratio. These four pins are labeled A20M#, IGNEE#, NMI, and INTR. It should be understood that when the Pentium.RTM. processor is in the RESET state, the clocking circuitry is stopped.
To provide more advanced processor clock signal control, it is desirable to change the internal clock frequency of the processor dynamically. In other words, there is an unsatisfied need for a processor capable of changing its internal clock frequency "on-the-fly"--obviating the need to reset the processor.
As will be seen, the present invention provides an apparatus and method for dynamically changing the clock frequency of a processor. This invention is advantageously suited for use in the mobile computing market, where it is desirable to quickly change the processor from one performance level to another. For example, the present invention permits the processor to operate in a high-power, high-performance state when docked in a fixture capable of supplying large amounts of power and external cooling. Alternatively, when the system is operating solely on battery power, such as would be the case in a mobile or laptop computer, the processor could enter a lower performance state which requires less power and cooling.